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Steady-state thermal mapping of electronic devices and circuits with multi-layer stack assembly by analytical relationships

DOI: 10.1615/ICHMT.2004.IntThermSciSemin.480
pages 413-420

M. Montesi
Dept. of Information Engineering, University of Pisa, Via Diotisalvi 2,I-56100 Pisa, Italy

Paolo Emilio Bagnoli
Dept. of Information Engineering, University of Pisa, Via Diotisalvi 2,I-56100 Pisa, Italy

G. Pasquinelli
Lab. Materials and Structures Mechanics I.S.T.I. "A. Faedo",C.N.R., via G. Moruzzi, I-56100 Pisa, Italy

C. Casarosa
Dept. of Energetics, University of Pisa, Via Diotisalvi 2, Pisa, Italy


This paper deals with an analytical model for the steady-state temperature mapping of electronic devices and system boards. It is devoted to solid structures which can be schematically modelled as a stack of several homogeneous layers of different materials and different sizes, also with various degree of asymmetry, and with two-dimensionally distributed heat generations. This mathematical model was implemented to replace conventional finite-elements (FEM) thermal simulators for fast thermal mappings, accurate within 1% and able to run in interaction with electrical and electro-thermal automatic design tools. His convenience in terms of speed and calculation amounts is due to the required 2-D meshing grids only at the interfaces instead of 3-D. The implemented thermal simulation program was validated by comparing the results of some virtual samples with the corresponding temperature and heat flux maps obtained with the FEM analysis. The amount and the origin of the error percentages with respect to the FEM analysis were also investigated as a functions of the free input parameters of the model.

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